Vlsi to you

Recently started to upload UVM(Universal verification methadolgy) videos in my youtube channel. Interested candidates can checkout this playlist for UVM tutorial.Will furthur upload all concepts of UVM here. UVM playlist: https://youtube.com/playlist?list=PLMn9V9QauiN4b1wgver4V3lqAhrnlKQqD&si=OFBB133AhZiESSqT To learn about UVM_REPORT_OBJECT checkout this video. https://youtu.be/mhlE7G-bbXY

Hey all, UVM_Hierarchy Is Important , but why??? Hierarchy is backbone of UVM organization This improves: # reuse # scalability # flexibility Without hierarchy: ❌ difficult debugging ❌ poor scalability ❌ messy communication ❌ hard configuration management Many beginners memorize components, but real understanding comes when you know how everything is connected inside the hierarchy. What is UVM Hierarchy? UVM hierarchy means the parent-child structure of components inside the testbench.Every component is connected in a structured way. Hierarchy helps in: ✅ component communication ✅ configuration passing ✅ phase execution ✅ debugging ✅ factory overrides ✅ reusability Without hierarchy, the testbench becomes difficult to manage. That’s why every verification engineer must clearly understand the UVM hierarchy. checkout this video for learning UVM_HIERARCHY in detail for UVM_void to UVM_components https://youtu.be/KYfyn0vDkm8?si=xlmvnF_wRdjjZ7Az

Uvm architecture: https://youtu.be/TtANfkRAYIA

To gain real-time hardware verification experience, you must build testbenches using industry-standard methodologies like Universal Verification Methodology (UVM) and SystemVerilog. The best resume-building projects involve testing standard protocols and complex architectures using constrained-random generation, coverage-driven testing, and scoreboards. To get idea on some good projects from basic to advanced level in DV domain checkout this video by clicking the link below. https://lnkd.in/gdkhtgrN Some playlists which may help you. APB PROTOCOL: https://lnkd.in/gAAipCZw SV TUTORIAL: https://lnkd.in/gU85Cx4d ASSERTIONS IN SV: https://lnkd.in/ewQYGtWB SV TESTBENCH DEVLOPMENT: https://lnkd.in/gxTnhjwF

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also as promised iam going to upload uvm series also soon. sorry for the delay as iam busy with tutoring sessions

hi everyone. many students are requesting me in linkedin and telegram also to give sv lectures in telugu which is why iam uploading sv series in telugu. if anyone are interested you can check this video by clicking the link https://youtu.be/Vos_0ku3h7w.

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Iam uploading the PDF of SV codes according to concepts in order.Also if you want to learn all these codes and learn how to develop Testbench codes then Iam offering Paid tutoring sessions. If anyone are interested you can contact me through linkedin id. I may not offer any certification to these courses but i will definitely help you to overcome your fear in developing the codes.

Hey all, Iam back uploading videos in my youtube channel. Sorry for the delay as Iam busy in tutoring sessions for students on verification courses. FIFO is an important concept in verilog as well as SV. So lets try to develop an SV TB code for FIFO from scratch. If you are intrested in writing an SV TB code for FIFO then check out this video by clicking the link below. FIFO TB DEVELOPMENT : https://youtu.be/Py3w0Rqqmbs Also to checkout this code i will link the address for the code below you can check it out. https://www.edaplayground.com/x/eMMy For more such content on both SV and UVM subscribe to my youtube channel. http://www.youtube.com/@SireeshaDevi-2127 Also if anyone are interested in my paid tutoring sessions you can contact me through linkedin.

This is my LinkedIn id https://www.linkedin.com/in/sireesha-devi-b22b8b281?utm_source=share&utm_campaign=share_via&utm_content=profile&utm_medium=android_app