fpga_news

https://spectrum.ieee.org/ai-chip-design

+ other insightful posts by Patrick Toulme https://patricktoulme.substack.com/

https://x.com/PatrickToulme/status/2017706776288719194

I rented a TPU V6e for under a dollar, dumped all the IR, and traced how it compiles JAX code all the way to emitted assembly. 8 lines of JAX → 250 VLIW bundles across 5 fused kernels. I walked through the full stack: HLO optimization, fusion, LLO lowering, and the final VLIW bundles. https://patricktoulme.substack.com/p/from-jax-to-vliw-tracing-a-computation src: https://www.linkedin.com/posts/patrick-toulme-150b041a5_from-jax-to-vliw-tracing-a-computation-through-activity-7410814951709265920-LFpY

https://www.tomshardware.com/tech-industry/semiconductors/worlds-first-thermodynamic-computing-chip-reaches-tape-out-normal-computings-physics-based-asic-changes-lanes-to-train-more-ai

Once again about TPU: Philosophy and Scaling https://henryhmko.github.io/posts/tpu/tpu.html

VeloxCon 2025 https://veloxcon.io/ Keynote Panel Hardware Accelerators: The Next 10x for Data Management https://www.youtube.com/watch?v=0WSuXCM2LV0

A start-up demonstrating LLM Inference on FPGA Altera Agilex 7M vs Nvidia H100 https://www.positron.ai/ looks pretty fantastic. there are probably some nuances and limitations...

#AMD #RDNA https://chipsandcheese.com/p/amds-rdna4-architecture-video

Thx to @cpu_design Author — Rahul B. at Tenstorrent "Here’s my list of 5 papers you should read to learn about Out-of-Order Processors!" #1 The Microarchitecture of Superscalar Processors by James E. Smith and Gurindar S. Sohi — Touches on every aspect of superscalar processor design and does an excellent job explaining concepts like register renaming, instruction scheduling, and memory operations. https://course.ece.cmu.edu/~ece447/s15/lib/exe/fetch.php?media=00476078.pdf #2 The Alpha 21264 Microprocessor by R. E. Kessler — Explains the instruction fetch, branch prediction, out-of-order execution, instruction retire and exceptions and the internal memory system for the Alpha 21264 processor. https://course.ece.cmu.edu/~ece447/s15/lib/exe/fetch.php?media=kessler_-_1999_-_the_alpha_21264_microprocessor.pdf #3 Implementing Precise Interrupts in Pipelined Processors by James E. Smith and Andrew R. Pleszkun — This paper does a great job at describing and evaluating solutions to the precise interrupt problem in pipelined processors. https://course.ece.cmu.edu/~ece447/s15/lib/exe/fetch.php?media=00004607.pdf #4 Checkpoint Repair for Out-of-order Execution Machines by Wen-mei W. Hwu and Yale N. Patt — Discusses the several properties for the checkpoint repair mechanism to reset the processor state to a known previous state. https://course.ece.cmu.edu/~ece447/s15/lib/exe/fetch.php?media=p18-hwu.pdf #5 A case for (partially) TAgged GEometric history length branch prediction by André Seznec and Pierre Michaud — This paper provides an excellent introduction to TAGE predictors, covering all relevant terminology along with hardware implementation details. https://www.irisa.fr/caps/people/seznec/JILP-COTTAGE.pdf

https://www.techradar.com/pro/microsoft-backed-a-tiny-hardware-startup-that-just-launched-its-first-ai-processor-that-does-inference-without-gpu-or-expensive-hbm-memory-and-a-key-nvidia-partner-is-collaborating-with-it

More about Tenstorrent architecture https://irrationalanalysis.substack.com/p/tenstorrent-and-the-state-of-ai-hardware

I'm excited to share a sneak peek of our latest work at Intel Corporation — a groundbreaking approach to Electronic Design Automation (EDA) that integrates intelligent design agents into the engineering workflow. Our agent, trained on massive datasets from the best of our engineers, provides real-time insights and solutions within the EDA tools, enabling the solving of tasks ranging from simple to complex multi-iteration challenges, making the design process more efficient and innovative. *This demo utilizes The OpenROAD Project, an open-source EDA tool developed by The Regents of the University of California. url: https://www.linkedin.com/posts/itai-yeshurun_intel-eda-llm-ugcPost-7267911435886682112-IIhh

Tenstorrent Wormhole Series Part 1: Physicalities Part 2: Which disabled rows? Part 3: NoC propagation delay Part 4: A touch of Ethernet Part 5: Taking apart T tiles Part 6: Vector instruction set Part 7: Bits of the MatMul https://tenstorrent.com/vision/community-highlight-tenstorrent-wormhole-series-part-1-physicalities

Let it be here. Life lessons from one of the greatest computer scientists. https://cacm.acm.org/opinion/life-lessons-from-the-first-half-century-of-my-career/

https://arxiv.org/abs/2409.03384

#MTIA https://engineering.fb.com/2024/08/22/ml-applications/meta-mtia-hardware-co-design/

https://www.cnbc.com/video/2024/08/23/how-google-makes-custom-cloud-chips-that-power-apple-ai-and-gemini.html